Bibliografia na stronach 857-865.

Chapter 1. Basic concepts and computer evolution: 1.1. Organization and architecture; 1.2. Structure and function; 1.3. The IAS Computer; 1.4. Gates, memory cells, chips and multichip modules; 1.5. The evolution of the Intel x86 architecture; 1.6. Embedded systems; 1.7. ARM architecture; 1.8. Key Terms, review questions, and problems; Chapter 2. Performance concepts: 2.1. Designing for performance; 2.2. Multicore, MICs and GPGPUs; 2.3. Two laws that provide insight: Ahmdahl’s Law and Little’s Law; 2.4. Basic measures of computer performance; 2.5. Calculating the mean; 2.6. Benchmarks and SPEC; 2.7. Key Terms, review questions, and problems; Part two: The computer systems: Chapter 3. A Top-level view of computer function and interconnection: 3.1. computer components; 3.2. computer function; 3.3. interconnection structures; 3.4. Bus interconnection; 3.5. Point-to-point interconnect; 3.6. PCI Express; 3.7. Key Terms, review questions, and problems; Chapter 4. The memory hierarchy: locality and performance: 4.1. Principle of loyalty; 4.2. Characteristics of memory systems; 4.3. The memory hierarchy; 4.4. Performance modeling of a multilevel memory hierarchy; 4.5. Key Terms, review questions, and problems; Chapter 5. Cache memory: 5.1. Cache memory principles; 5.2. Elements of cache designs; 5.3. Intel x86 cache organization; 5.4. The IBM z13 cache organization; 5.5. Cache performance models; 5.6. Key Terms, review questions, and problems; Chapter 6. Internal memory: 6.1. Semiconductor main memory; 6.2. Error correction; 6.3. DDR DRAM; 6.4. eDRAM; 6.5. Flash memory; 6.6. Newer Nonvolatile solid-state memory technologies; 6.7. Key Terms, review questions, and problems; Chapter 7. External memory: 7.1. Magnetic disk; 7.2. RAID; 7.3. Solid state drives; 7.4. Optical memory; 7.5. Magnetic tape; 7.6. Key Terms, review questions, and problems; Chapter 8. Input/Output: 8.1. External devices; 8.2. I/O Modules; 8.3. Programmed I/O; 8.4. Interrupt-driven I/O; 8.5. Direct memory access; 8.6. Direct cache access; 8.7. I/O channels and processors; 8.8. External interconnection standards; 8.9. IBM z13 I/O structure; 8.10. Key Terms, review questions, and problems; Chapter 9. Operating systems support: 9.1. Operating system overview; 9.2. Scheduling. 9.3. Memory management; 9.4. Intel x86 Memory management; 9.5. ARM Memory Management; 9.6. Key Terms, review questions, and problems; Part Three: Arithmetic and logic: Chapter 10. Number systems: 10.1. The decimal system; 10.2. Positional number systems; 10.3. The binary system; 10.4. converting between binary and decimal; 10.5. Hexadecimal notation; 10.6. Key Terms and problems; Chapter 11. Computer Arithmetic: 11.1. The arithmetic and logic unit; 11.2. Integer representation; 11.3. integer arithmetic; 11.4. Floating-point representation; 11.5. Floating-point arithmetic; 11.6. Key Terms, review questions, and problems; Chapter 12. Digital Logic: 12.1. Boolean algebra; 12.2. Gates; 12.3. Combinational circuits; 12.4. Sequential circuits; 12.5. Programmable logic devices; 12.6. Key Terms, review questions, and problems; Part Four: Instruction sets and assembly language: Chapter 13. Instruction sets: characteristics and functions: 13.1. Machine instruction characteristics; 13.2. Types of Operands; 13.3. Intel x86 and ARM data types; 13.4. Types of organizations; 13.5. Intel x86 and ARM operation types; 13.6. Key Terms, review questions, and problems; Appentix 13A Little-, Big-, and Bi-Endian; Chapter 14. Instruction sets: addressing modes and formats: 14.1. Addressing Modes; 14.2. x86 and ARM Addressing modes; 14.3. Instruction formats; 14.4. x86 and ARM Instructions formats; 14.5. Key Terms, review questions, and problems; Chapter 15.Assembly Language and Related Topics: 15.1. Assembly language concepts; 15.2. Motivation for assembly language programming; 15.3. Assembly language elements; 15.4. Examples; 15.5. Types of assemblers; 15.6. Assemblers; 15.7. Loading and Linking; 15.8. Key Terms, review questions, and problems; Part Five: The central processing unit: Chapter 16. Processor structure and function: 16.1. Processor organization; 16.2. Register organization; 16.3. Instruction cycle; 16.4. Instruction pipelining; 16.5. Processor organization for pipelining; 16.6. The x86 processor family; 16.7. The ARM processor; 16.8. Key Terms, review questions, and problems; Chapter 17. Reduced instruction set computers: 17.1. Instruction execution characteristics; 17.2. The use of a large register file; 17.3. Compiler-based register optimization; 17.4. Reduced instruction set architecture; 17.5. RISC Pipelining; 17.6. MIPS R4000; 17.7. SPARC; 17.8. Processor organization for pipelining; 17.9. CISC, RISC, and contemporary systems; 17.10. Key Terms, review questions, and problems; Chapter 18. Instruction-Level Parallelism and Superscalar processors: 18.1. Overview; 18.2. Design Issues; 18.3. Intel Core Microarchitecture; 18.4. ARM Cortex-A8; 18.5. ARM Cortex-M3; 18.6. Key Terms, review questions, and problems; Chapter 19. Control Unit operation and microprogrammed control: 19.1. Micro-operations; 19.2. Control of the processor; 19.3. Hardwired implementation; 19.4. Microprogrammed control; 19.5. Key Terms, review questions, and problems; Part Six: Parallel organization: Chapter 20. Parallel Processing: 20.1. Multiple processors organization; 20.2. Symmetric Multiprocessors; 20.3. Cache Coherence and the MESI protocol; 20.4. Multithreading and chip multiprocessors; 20.5. Clusters; 20.6. Nonuniform memory access; 20.7 Key Terms, review questions, and problems; Chapter 21. Multicore computers: 21.1. Hardware performance issues; 21.2. Software performance issues; 21.3. Multicore organization; 21.4. Heterogeneous multicore organization; 21.5. Intel Core i7-5960X; 21.6. ARM Cortex-A15 MPCore; 21.7. IBM z13 Mainframe; 21.8. Key Terms, review questions, and problems; Appendix A. System Buses: A.1. Bus structure; A.2. Multiple-bus hierarchies; A.3. Elements of bus design; Appendix B. Victim Cache strategies: B.1. Victim Cache; B.2. Selective victim cache; Appendix C. Interleaves memory; Appendix D. The international reference alphabet; Appendix E. Stacks; E.1. Stacks; E.2. Stack implementation; E.3. Expression evaluation; Appendix F. Recursive procedures: F.1. Recursion; F.2. Activation Tree representation; F.3. Stack implementation; F.4. Recursion and Iteration; Appendix G. Additional Instruction Pipeline topics: G.1 Pipeline reservation tables; G.2. Reorder Buffers; G.3. Tomasulo’s Algorithm; G.4. Scoreboarding.